ICSSSTUB32871A Datasheet, PDF (15/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
3 Test circuits and switching waveforms (cont’d)
3.3 Error output load circuit and voltage measurement information (V_DD = 1.8 V ± 0.1 V)
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z_o = 50Ω ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
DUT
Out
V_DD
C_L = 10 pF
(see Note 1)
R_L = 1KΩ
Test Point
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
(1) C_L includes probe and jig capacitance.
Figure 28 — Load circuit, error output measurements
LVCMOS
RST
Input
t _PLH
Output
Waveform 2
VCC /2
V CC
0V
VOH
_ _0.1_5 _V _ _ _ _ _ _ _ _{0 V}
Figure 29 — Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
Timing
Inputs
tPHL
Output
Waveform 1
VICR
VICR
VI(PP)
_ _ _ _ _ _ _ _ _ _ _ _{V CC}
V _CC /2
V _OL
Figure 30 — Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
Timing
Inputs
tPHL
Output
Waveform 2
VICR
VICR
0.15 V
VI(PP)
V _OH
0V
Figure 31 — Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
1186G—04/16/07
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