ICSSSTUB32871A Datasheet, PDF (13/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
CK Inputs
TL=50Ω
Test Point
R_L = 100Ω
Test Point
DUT
TL=350ps, 50Ω
CK _Out
CK
C_L = 30 pF
(see Note 1)
LOAD CIRCUIT
VDD
R_L = 1000Ω
Test Point
R_L = 1000Ω
VCMOS
RST
Inp ut
V_DD/2
V_DD/2
V_DD
0V
t _{in act}
t_act
I_DD
(see
Note 2)
10%
90%
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
t_w
V_ID
Inpu t
V_ICR
V_ICR
VOLTAGE WAVEFORMS – PULSE DURATION
V_ID
CK
V_ICR
CK
t_su
t_h
Inpu t
V_REF
V_IH
V_REF
V_IL
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
CK
V_ICR
CK
V_ID
V_ICR
t_PLH
t_PHL
Ou t put
V_TT
V_OH
V_TT
V_OL
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
LVCMOS
V_IH
RST
V_DD/2
In put
V_IL
t_RPHL
Ou t p u t
V_OH
V_TT
V_OL
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
Figure 6 — Parameter Measurement Information (V_DD = 1.8V^± 0.1V)
Notes: 1. C_L incluces probe and jig capacitance.
2. I_DD tested with clock and data inputs held at V_DD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V_REF = V_DD/2
6. V_IH = V_REF + 250 mV (ac voltage levels) for differential inputs. V_IH = V_DD for LVCMOS input.
7. V_IL = V_REF - 250 mV (ac voltage levels) for differential inputs. V_IL = GND for LVCMOS input.
8. V_ID = 600 mV
9. t_PLH and t_PHL are the same as t_PDM.
1186G—04/16/07
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