ICSSSTUB32871A Datasheet, PDF (6/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
Parity Functionality Block Diagram
21
21
Dn
DQ
D
PARIN
D
CLOCK
Qn
D
LATCHING AND
RESET FUNCTION
see Note (1)
PTYERR
(1) This function holds the error for two
cycles. See functional description and
timing diagram.
002aaa417
1186G—04/16/07
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