ICSSSTUB32871A Datasheet, PDF (8/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
Register Timing
RESET
DCSn
CK
n
n+1
n+2
n+3
n+4
CK
Dn ⁽¹⁾
Qn
PARIN
tsu
th
tPDM, tPDMSS
CK to Q
tsu
th
PTYERR
Unknown input event
Output signal is dependent on the piorr unknown event
Figure 5 — RESET being held HIGH
tPHL, tPLH
CK to PTYERR
H or L
002aaa984
1186G—04/16/07
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