ICSSSTUB32871A Datasheet, PDF (18/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
Revision History
Rev. Issue Date Description
Page #
B
3/20/2006 Updated Ordering Information.
17
C
2/2/2007
Applications, 2nd bullet, changed ULP877 to ULPA877A, added
IDTCSPUA877A
1
Page 1, Applications, 3rd bullet, removed 800; page 11, Electrical table,
D
3/1/2007 ^{changed Idd Operating Max from 80 to 150, changed RESET Typ from 2.5} 1, 11, 12
to 4.5; page 12, Timing table, changed ts (Data before...) from 0.5 to 0.6,
changed th (DCS, DODT...) from 0.5 t
E
3/6/2007 ^{Timing table, th hold time, changed Q to Dn; Switching Cha. Table, fixed}
12
typos.
Page 1, Recc. List, changed 3rd bullet to "Provides complete DDR DIMM
F
3/13/2007 solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A"; page 1, 11
11, fixed typos.
G
4/16/2007 ^{Electrical Cha. Table, changed Ci: Data Inputs max from 3.5 to 5, and}
11
CLK Max from 3 to 3.8.
1186G—04/16/07
18