ICSSSTUB32871A Datasheet, PDF (3/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
General Description
This 27-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V V_DD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are
LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load.
The ICSSSTUB32871A operates from a differential clock (CK and CK). Data are registered at the crossing of CK
going high, and CK going low.
The device supports low-power standby operation. When the reset input (RESET) is low, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are
allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced
low. The LVCMOS RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held
in the low state during power up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK
and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the
register will be cleared and the outputs will be driven low quickly, relative to the time to disable the
differential input receivers. However, when coming out of reset, the register will become active quickly,
relative to the time to enable the differential input receivers. As long as the data inputs are low, and the
clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully
enabled, the design of the ICSSSTUB32871A must ensure that the outputs will remain low, thus ensuring no
glitches on the output.
The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when
both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function
normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs
low and the PTYERR output high. If the DCS-control functionality is not desired, then the CSGateEnable
input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as
for the other D data inputs.
The ICSSSTU32871A includes a parity checking function. The ICSSSTUB32871A accepts a parity bit from the
memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
Package options include 96-ball Thin Profile Fine Pitch BGA (TFBGA, MO-TBD).
Inputs
Output
RESET DCS0
DCS1
CK
CK
of inputs = H
(D0-D21)
H
L
H
↑
↓
Even
H
L
H
H
L
H
↑
↓
↑
↓
Odd
Even
H
L
H
↑
↓
Odd
H
H
L
H
H
L
↑
↓
↑
↓
Even
Odd
H
H
L
H
H
L
↑
↓
↑
↓
Even
Odd
H
H
H
↑
↓
X
H
X
X
L or H
L or H
X
L
X or
floating
X or
floating
X or
floating
X or
floating
X or floating
* PARIN arrives one clock cycle after the data to which it applies.
PARIN* PTYERR**
L
L
H
H
L
L
H
H
X
X
X or
floating
H
L
L
H
H
L
L
H
PTYERR₀
PTYERR ₀
H
** This transition assumes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR
is low, it stays latched low for two clock cycles or until RESET is driven low.
1186G—04/16/07
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