ICSSSTUB32871A Datasheet, PDF (7/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
Register Timing
RESET
DCSn
CK
CK
Dn ⁽¹⁾
Qn
PARIN
PTYERR
tACT
n
n+1
n+2
n+3
n+4
tsu
th
tPDM, tPDMSS
CK to Q
tsu
th
tPHL
CK to PTYERR
tPHL, tPLH
CK to PTYERR
H, L, or X
H or L
Figure 4 —RESET switches from L to H
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a
minimum time of t_ACT (max) to avoid false error.
1186G—04/16/07
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