ICSSSTUB32871A Datasheet, PDF (11/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
Electrical Characteristics - DC
T_A = 0 - 70°C; V_DD = 2.5 +/-0.2V, V_DDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL PARAMETERS
CONDITIONS
V_DDQ MIN
V_OH
I_OH = -8mA
1.7V 1.2
V_OL
I_OL = 8mA
1.7V
I_I All Inputs
V_I = V_DD or GND
Standby (Static) RESET = GND
1.9V
I_DD
Operating (Static) ^{VI = VIH(AC) or VIL(AC),}
RESET = V_DD
1.9V
Dynamic operating
(clock only)
RESET = V_DD,V_I = V_IH(AC)
or V_IL(AC), CLK and CLK
switching 50% duty cycle.
I_O = 0
I_DDD
RESET = V_DD, V_I = V_IH(AC)
Dynamic Operating ^{or VIL (AC), CLK and CLK}
(per each data
switching 50% duty cycle.
input)
One data input switching
at half clock frequency,
1.8V
50% duty cycle
Data Inputs
V_I = V_REF ±350mV
2.5
C_i CLK and CLK
V_ICR = 1.25V, V_I(PP) = 360mV
2
RESET
V_I = V_DDQ or GND
Notes:
1 - Guaranteed by design, not 100% tested in production.
TYP MAX
0.5
±5
200
150
UNITS
V
µA
µA
mA
TBD
µA/clock
MHz
TBD
µA/ clock
MHz/data
5
pF
3.8
4.5
pF
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
PARAMETER
V_DD = 1.8V ± 0.1V
MIN
MAX
UNIT
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
dV/dt_Δ¹
1
V/ns
V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
1186G—04/16/07
11