ICSSSTUB32871A Datasheet, PDF (1/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

Integrated
Circuit
Systems, Inc.
ICSSSTUB32871A
27-Bit Registered Buffer for DDR2
Recommended Application:
Pin Configuration
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A
123456
A
• Optimized for DDR2 400/533/667 JEDEC 4 Rank
B
VLP DIMMS
C
D
Product Features:
E
F
• 27-bit 1:1 registered buffer with parity check
functionality
G
• Supports SSTL_18 JEDEC specification on data
H
inputs and outputs
J
• Supports LVCMOS switching levels on RESET input
K
• 50% more dynamic driver strength than standard
L
SSTU32864
M
• Low voltage operation
N
V_DD = 1.7V to 1.9V
P
• Available in 96 BGA package
R
T
96 Ball BGA
(Top View)
Functionality Truth Table
In puts
Outputs
RESET
DCS0
DCS1
CSGate
Enable
CK
Dn,
CK DODTn, Qn
DCK En
H
L
L
X
↑
↓
L
L
H
L
L
X
↑
↓
H
H
H
L
L
X
L or H L or H
X
Q₀
H
L
H
X
↑
↓
L
L
H
L
H
X
↑
↓
H
H
H
L
H
X
L or H L or H
X
Q₀
H
H
L
X
↑
↓
L
L
H
H
L
X
↑
↓
H
H
H
H
L
X
L or H L or H
X
Q₀
H
H
H
L
↑
↓
L
L
H
H
H
L
↑
↓
H
H
H
H
H
L
L or H L or H
X
Q₀
H
H
H
H
↑
↓
L
Q₀
H
H
H
H
↑
↓
H
Q₀
H
H
H
H
L or H L or H
X
Q₀
L
X or
X or
X or
X or
X or
X or
floating floating floating floating floating floating
L
QCS
QODT,
QCKE
L
L
L
H
Q₀
Q₀
L
L
L
H
Q₀
Q₀
H
L
H
H
Q₀
Q₀
H
L
H
H
Q₀
Q₀
H
L
H
H
Q₀
Q₀
L
L
1186G—04/16/07