ICSSSTUB32871A Datasheet, PDF (12/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
VDD = 1.8V ±0.1V
MIN MAX
f_clock
t_W
t_ACT
Clock frequency
Pulse duration
Differential inputs active time
410
1
10
t_INACT Differential inputs inactive time
15
t_S
Setup time
Hold time
t_H
Hold time
Data before CLK↑, CLK↓
0.6
DCS0, DSC1 before CLK↑,
CLK↓, CSR HIGH
0.7
DCS, DODT, DCKE and Dn
after CLK↑, CLK↓
0.6
PAR_IN after CLK↑, CLK↓
0.5
UNITS
MHz
ns
ns
ns
ns
ns
ns
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CLK/CLK signal input slew rate of 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN MAX
fmax Max input clock frequency
410
t_PDM
Propagation delay, single _{CLK↑ and CLK↓ to Qn}
bit switching
t_LH
Low to High propagation CLK↑ and CLK↓ to
delay
PTYERR
t_HL
High to low propagation
delay
CLK↑ and CLK↓ to
PTYERR
1.25 1.9
1.2
3
0.9
3
t_PDMSS
Propagation delay
simultaneous switching
CLK↑ and CLK↓ to Qn
2
t_PHL
High to low propagation
delay
RESET ↓ to Qn↓
3
t_PLH
Low to High propagation
delay
RESET ↓ to PTYERR↑
3
1. Guaranteed by design, not 100% tested in production.
Units
MHz
ns
ns
ns
ns
ns
ns
1186G—04/16/07
12