ICSSSTUB32871A Datasheet, PDF (16/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
3 Test circuits and switching waveforms (cont’d)
3.4 Partial-parity-out load circuit and voltage measurement information (V_DD = 1.8 V ± 0.1 V)
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z_o = 50Ω ; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
DUT
Out
CL = 5 pF
(see Note A)
Test Point
RL = 1 kΩ
(1) C_L includes probe and jig capacitance.
Figure 32 — Partial-parity-out load circuit,
CK
VICR
CK
tPLH
VICR
tPHL
Vi(p-p)
OUTPUT
VTT
VOH
VOL
002aaa375
V_TT = V_DD/2
t_PLH and t_PHL are the same as t_PD.
V_I(PP) = 600 mV
Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
LVCMOS RST
INPUT
OUTPUT
VDD/2
tPHL
VIH
VIL
VOH
VTT
VOL
002aaa376
V_TT = V_DD/2
t_PLH and t_PHL are the same as t_PD.
V_IH = V_REF + 250 mV (AC voltage levels) for differential inputs. V_IH = V_DD for LVCMOS inputs.
V_IL = V_REF - 250 mV (AC voltage levels) for differential inputs. V_IL = V_DD for LVCMOS inputs.
Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
1186G—04/16/07
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