ICS1524 Datasheet, PDF (9/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Name: DPA Control Register
Register: 5h
Index: Read / Write*
Bit Name
DPA_Res 0-1
Metal_Rev
Bit #
0-1
2-7
Reset Value
3
0
Description
Dynamic Phase Adjust Resolution Select.
Metal Mask Revision Number.
Bit Name
Description
0-1 DPA_Res 0 -1 Dynamic Phase Adjust (DPA) Resolution Select.
It is not recommended to use the DPA above 160 MHz.
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Delay Elements
16
32
Reserved
64
12
CLK Range, MHz
48
160
24
80
40
2-7 Metal_Rev
Metal Mask Revision Number.
After power-up, register bits 7:2 must be written with 111111. After this write,
a read indicates the metal mask revision, as below.
Revision
A
B
C1
C2
D
E
F
G
Bit 7
1
0
1
0
1
1
1
1
Bit 6
1
1
0
0
1
1
1
1
Bit 5
1
1
1
1
0
1
1
1
Bit 4
1
1
1
1
1
0
1
1
Bit 3
1
1
1
1
1
1
0
1
Bit 2
1
1
1
1
1
1
1
0
* ^{Double-buffered register. Actual working registers are loaded during software DPA reset.}
See register 8h for details.
ICS1524 Rev C 01/31/2003
9