ICS1524 Datasheet, PDF (3/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

OSC
(12)
HSYNC
(7)
PDEN (5)
Osc_Div
Reg 7:0-6
Osc
Divider
Ref_Pol
Reg 0:2
1
MUX
0
EXTFB
(6)
Fbk_Sel
Reg 0:4
1
MUX
0
Fbk_Pol
Reg 0:3
SDA
(3)
SCL
(4)
I²CADR
(13)
I²C
Interface
Power-
On
Reset
PD_Pol
Reg 0:1
LOCK/REF (14)
PDen
Reg 0:0
Lock
Logic
En_DLS
Reg 0:7 EXTFIL (8) XFILRET (9)
En_PLS
Reg 0:6
Phase/
Freq
Detector
PLL_Lock
PFD Reg 12:1
Reg 1:0-2
Charge
Pump
Filter
Select
Fil_Sel
Reg 4:7
Int Filter
VCO
PECL
Bias
Post-
Scaler
Divider
PSD
Reg 1:4-5
Out_Scl
Reg 6:6-7
IREF
(24)
Feedback
Divider
FDB1
FDB0 ^{Reg: 3:0-3}
2:0-7
Reg
Func_Sel
Reg 0:5
1
MUX
0
DPA_Lock
Reg 12:0
Output
Scaler
DPA_OS
Reg 4:0-5
DPA_Res
Reg 5:0-1
Dynamic
Phase
Adjust
1
MUX
0
Ck2_Inv
Reg 6:5
DPACLK (17)
OE_Tck
Reg 6:1
+
DPACLK+ (21)
DPACLK– (20)
OE-Pck
Reg 6:0
CLK (16)
OE_T2
Reg 6:3
+
CLK+ (23)
CLK– (22)
OE_P2
Reg 6:2
FUNC (15)
OE_F
Reg 6:4
ICS1524 Block Diagram
June 25, 2001