ICS1524 Datasheet, PDF (20/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
DPA Delay-16 Element Resolution
20
18
16
50 MHz - SVGA @ 72 Hz
14
157.5 MHz - SXGA @ 85 Hz
12
10
8
6
4
2
0
0
4
8
12
16
DPA Setting
DPA Delay - 32 Element Resolution
45
40
35
25.175 MHz - VGA @ 60 Hz
30
78.75 MHz - XGA @ 75 Hz
25
20
15
10
5
0
0
4
8
12
16
20
24
28
32
DPA Setting
DPA Delay - 64 Element Resolution
90
80
70
60
50
40
30
20
10
0
0
12.27 MHz - NTSC
39.8 MHz - SVGA @ 60
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
DPA Setting
Note:
Maximum number of data points used for this graph.
ICS1524 Rev C 01/31/2003
20