ICS1524 Datasheet, PDF (10/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Name: Output Enable Register
Register: 6 h
Index: Read / Write
Bit Name Bit # Reset Value Description
OE_Pck
0
OE_Tck
1
OE_P2
2
OE_T2
3
OE_F
4
Sel_1X
5
Out_Scl
6-7
0
Output Enable for DPACLK Outputs (PECL, Pins 21, 20 )
0
Output Enable for DPACLK Output (SSTL_3 Pin 17)
0
Output Enable for CLK Outputs (PECL, Pins 23, 22)
0
Output Enable for CLK Output (SSTL_3, Pin 16)
0
Output Enable for FUNC Output (SSTL_3, Pin 15)
0
Select CLK Output Source (Pins 23, 22, 16)
0
CLK Output Scaler (SSTL_3, Pin 16)
Bit
Name
0
OE_Pck
1
OE_Tck
2
OE_P2
3
OE_T2
4
OE_F
5
Ck2_Inv
6 -7
Out_Scl
Description
Output Enable for DPACLK Outputs (PECL)
0 = High Z
1 = Enabled
Output Enable for DPACLK Output (SSTL_3)
0 = High Z
1 = Enabled
Output Enable for CLK Outputs (PECL)
0 = High Z
1 = Enabled
Output Enable for CLK Output (SSTL_3)
0 = High Z
1 = Enabled
Output Enable for FUNC Output (SSTL_3)
0 = High Z
1 = Enabled
Select CLK Output Source (Pins 23, 22, 16)
0 = Half Speed DPA Delayed clock to CLK outputs
1 = Full Speed non-DPA Delayed clock to CLK outputs
Clock (CLK, pin 16) Scaler
Bit 7
0
0
1
1
Bit 6
0
1
0
1
CLK Divider
1
2
4
8
ICS1524 Rev C 01/31/2003
10