ICS1524 Datasheet, PDF (12/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Name: Chip Version Register
Register: 10 h
Index: Read
Bit Name Bit # Reset Value Description
Chip Ver
0-7
17
Chip Version 24 (18h )
Name: Chip Revision Register
Register: 11h
Index: Read
Bit Name Bit # Reset Value Description
Chip Rev
0 -7
01+
Initial value 01h.
+Value increments with each all-layer change.
Name:
Register:
Index:
Bit Name
DPA_Lock
PLL_Lock
Reserved
Status Register
12 h
Read
Bit # Reset Value
0
N /A
1
N /A
2 -7
0
Description
DPA Lock Status
PLL Lock Status
Reserved
Bit
Name
Description
0
DPA_Lock
DPA Lock Status. (Refer to Register 0h, bits 6 and 7.)
0 = Unlocked
1 = Locked
1
PLL_Lock
PLL Lock Status. (Refer to Register 0h, bits 6 and 7.)
0 = Unlocked
1 = Locked
2 -7
Reserved
ICS1524 Rev C 01/31/2003
12