ICS1524 Datasheet, PDF (14/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
I²C Data Format
RANDOM REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 x WA
7 bit address
START condition
register address
Acknowledge
WRITE command
A
data
Acknowledge
AP
STOP condition
Acknowledge
RANDOM REGISTER READ PROCEDURE
S 0 1 0 0 1 1 XWA
7 bit address
START condition
register address
Acknowledge
WRITE command
AS 0 1 0 0 1 1 XRA
7 bit address
Repeat START
Acknowledge
data
Acknowledge
READ command
AP
STOP condition
NO Acknowledge
SEQUENTIAL REGISTER WRITE PROCEDURE
S 0 1 0 0 1 1 XWA
7 bit address
START condition
register address
Acknowledge
WRITE command
A
data
Acknowledge
A
data
Acknowledge
A
AP
Acknowledge Acknowledge
STOP condition
SEQUENTIAL REGISTER READ PROCEDURE
S 0 1 0 0 1 1 XWA
7 bit address
START condition
register address
Acknowledge
WRITE command
AS 0 1 0 0 1 1 XRA
7 bit address
Repeat START
Acknowledge
data
Acknowledge
READ command
A
AP
data
NO Acknowledge
Acknowledge STOP condition
Direction: From bus host to device
From device to bus host
Note:
1. All values are transmitted with the most-significant bit first and the least-significant bit last.
2. The value of the X bit equals the logic state of pin 13 (I²CADR).
3. R = READ = 1 and W = WRITE = 0
ICS1524 Rev C 01/31/2003
14