ICS1524 Datasheet, PDF (17/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Power Supply Considerations
The ICS1524 incorporates special internal power-on reset circuitry that requires no external reset signal connection. The sup-
ply voltage (VDD) must remain within the recommended operating conditions during normal operation. To reset the ICS1524,
the supply voltage at the part must be reduced below the threshold voltage (V_th) of the power-on reset circuit. The supply volt-
age must remain below that threshold voltage such that board power conditioning capacitors are drained and the proper reset
state is latched. The amount of time (t_d) to hold the voltage in a reset state varies with the design. However, a typical value of
10 ms should be sufficient.
Supply
Voltage
Vmin
td
Vth = 1.8V
Absolute Maximum Ratings
VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . . 4.3V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3V to 5.5V
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSA – 0.3V to VDDA +0.3V
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSSQ – 0.3V to VDDQ +0.3V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD Susceptibility* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV
(*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)
ICS1524 Rev C 01/31/2003
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