ICS1524 Datasheet, PDF (21/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
HSYNC
REF
PECL CLK-
PECL CLK+
SSTL-CLK
FUNC_OUT
t0
tR
tS
t1
tF
t5
t2
t4
t3
t8
tp
t9
PECL DPACLK-
PECL DPACLK+
SSTL-DPACLK
FUNC
t_DPA
t1
t2
t3
tp
tS
t4
tF
t8
t9
Typical Transition Times*
Symbol
Timing Description
t_R REF
t_P PECL CLK
t_S SSTL-CLK
t_F FUNC_OUT
Rise Fall Units
2.8 1.8 ns
1.0 1.2 ns
1.6 0.7 ns
1.2 1.0 ns
Output Timing*
Symbol
Timing Description
Min Typ Max Units
t₀ HSYNC to REF delay
11.3 11.5 12 ns
t₁ REF to PECL clock delay
-1.0 0.8 2.2 ns
t₂, t₃ PECL clock duty cycle
45 50 55 %
t₄ PECL clock to SSTL_3 clock delay
0.2 0.75 1.2 ns
t₅ PECL clock to FUNC_OUT delay
1.5 1.9 2.3 ns
t₆ PECL clock to PECL/2 clock
1.0 1.3 1.5 ns
t₇ PECL clock to SSTL_3–CLK/2 delay 1.1 1.4 1.8 ns
t₈, t₉ SSTL clock duty cycle
45 50 55 %
*Note: Measured at 3.6V 0°C, 135-MHz output frequency, PECL clock lines to 75 Οηµ termination, SSTL_3 clock lines
unterminated, 20-pF load. Transition times vary based on termination.
ICS1524 Rev C 01/31/2003
21