ICS1524 Datasheet, PDF (7/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Name: Loop Control Register
Register: 1h
Index: Read / Write*
Bit Name Bit # Reset Value Description
PFD 0 -2
0-2
Reserved
3
PSD 0-1
4-5
Reserved 6 -7
0
Phase Frequency Detector Gain
0
Reserved
0
Post-Scaler Divider
0
Reserved
Bit Name
0-2 PFD0-2
Description
Phase/Frequency Detector Gain
Bit 2
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
Bit 0
0
1
0
1
0
1
0
1
PFD Gain (µA/2π rad)
1
2
4
8
16
32
64
128
3 Reserved
4-5 PSD 0-1
Post-Scaler Divider — Divides the output of the VCO to the DPA and Feedback Divider.
Bit 5
0
0
1
1
Bit 4
0
1
0
1
PSD Divider
2 (default)
4
8
16
6-7 Reserved
*^{Double-buffered register. Actual working registers are loaded during software PLL reset.}
See register 8h for details.
ICS1524 Rev C 01/31/2003
7