ICS1524 Datasheet, PDF (11/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Name: Oscillator Divider Register
Register: 7h
Index: Read / Write
Bit Name
Osc_Div 0-6
In_Sel
Bit #
0-6
7
Reset Value
0
1
Description
Osc Divider Modulus
Input Select
Bit
Name
Description
0-6
Osc_Div 0-6 Oscillator Divider Modulus.
Divides the input from OSC (pin 12) by the set modulus.
The modulus equals the programmed value, plus 2.
Therefore, the modulus range is from 3 to 129.
7
In_Sel
Input Select — Selects the input to the Phase/Frequency Detector
0 = HSYNC
1 = Osc Divider
Name: RESET Register
Register: 8 h
Index: Write
Bit Name
DPA Reset
PLL Reset
Bit #
0-3
4 -7
Reset Value
x
x
Description
Writing xAh to this register resets DPA working register 5
Writing 5xh to this register resets PLL working registers 1-3
Bit
Name
0 -3
DPA
4 -7
PLL
Description
Writing xAh to this register resets DPA working register 5
Writing 5xh to this register resets PLL working registers 1-3
Value
xA
5x
5A
Resets
DPA
PLL
DPA and PLL
ICS1524 Rev C 01/31/2003
11