ICS1524 Datasheet, PDF (4/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Pin Descriptions
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
PIN NAME
VDDD
VSSD
SDA
SCL
PDEN
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
13
I²CADR
14
LOCK/REF
15
FUNC
16
CLK
17
DPACLK
18
VDDQ
19
VSSQ
20
DPACLK–
21
DPACLK+
22
CLK–
23
CLK+
24
IREF
TYPE
PWR
PWR
IN/OUT
IN
IN
IN
IN
IN
IN
PWR
PWR
IN
IN
SSTL
SSTL
SSTL
SSTL
PWR
PWR
PECL
PECL
PECL
PECL
IN
DESCRIPTION
Digital supply
Digital ground
Serial data
Serial clock
PFD enable
External feedback
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
I²C address
Lock indicator/reference
Function output
Pixel clockt
DPA Delayed Clock
Output driver supply
Output driver ground
DPA Delayed PECL clock -
DPA Delayed PECL clock +
PECL clock -
PECL clock +
Reference current
COMMENTS
3.3V to digital sections
Ground for digital sections
I²C-bus¹
I²C-bus¹
Suspends charge pump¹
External divider input to PFD¹
Clock input to PLL¹
External PLL loop filter
External PLL loop filter return
3.3V for analog circuitry
Ground for analog circuitry
Input from crystal oscillator package^{1, 2}
Chip I²C address select
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
Displays PLL or DPA lock or REF input
SSTL_3 selectable HSYNC output
Non-Delayed SSTL_3 Clock
DPA Delayed SSTL_3 Clock
3.3V VDD for output drivers
Ground for output drivers
DPA Delayed Inverted PECL Clock Open drain.
DPA Delayed PECL Clock
Open drain.
Non-Delayed Inverted PECL Clock Open drain.
Non-Delayed PECL Clock
Open drain.
Reference current for PECL outputs
Notes:
1. These LVTTL inputs are 5 V-tolerant.
2. Connect to ground if unused.
ICS1524 Rev C 01/31/2003
4