ICS1524 Datasheet, PDF (18/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Recommended Operating Conditions
VDD, VDDQ, VDDA (measured to VSS) . 3.0 to 3.6 V
Operating Temperature (Ambient) . . . . . . 0 to +70°C
DC Supply Current
PARAMETER
Supply Current, Digital
Supply Current, Output Drivers
Supply Current, Analog
SYMBOL
IDDD
IDDQ
IDDA
CONDITIONS
VDDD = 3.6V
VDDQ = 3.6V, no output drivers enabled.
VDDA = 3.6V
MIN
—
—
—
MAX
25
6
5
UNITS
mA
mA
mA
Digital Inputs (SDA, SCL, PDEN, EXTFB, HSYNC, OSC, I²CADR)
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
Input High Current
Input Low Current
Input Capacitance
IIH
V_IH = VDD
IIL
V_IL = 0
Cin
MIN
2
VSS-0.3
0.2
—
—
—
MAX
5.5
0.8
0.6
±10
±200
10
UNITS
V
V
V
µA
µA
pF
SDA (In Output Mode: SDA is Bidirectional)
PARAMETER
SYMBOL
CONDITIONS
Output Low Voltage
VOL
IOUT = 3 mA. VOH = 6.0V maximum as
determined by the external pull-up resistor.
MIN
MAX UNITS
0.4
V
PECL Outputs (DPACLK+, DPACLK–, CLK+, CLK -)
PARAMETER
SYMBOL
CONDITIONS
Output High Voltage
VOH IOUT = 0
Maximum Output Frequency
Fp MAX VDDD = 3.3V
Output Low Voltage
(Note: VOL must not fall below
the level given so that the correct
value for IOUT can be
maintained.)
VOL IOUT = programmed value
MIN
—
—
MAX
VDD
250
UNITS
V
MHz
1.0
—
V
SSTL-3 Outputs (DPACLK, CLK, FUNC, LOCK/REF)
PARAMETER
SYMBOL
CONDITIONS
Output Resistance
Maximum Output Frequency
R_O
1 <V_O<2V
Fs MAX VDDD = 3.3V
MIN
—
—
MAX
80
150
UNITS
Ω
MHz
AC Input Characteristics
PARAMETER
HSYNC Input Frequency
OSC Input Frequency
SYMBOL
f_HSYNC
f_OSC
CONDITIONS
MIN
.008
.02
MAX
10
100
UNITS
MHz
MHz
ICS1524 Rev C 01/31/2003
18