ICS1524 Datasheet, PDF (1/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

Integrated
Circuit
Systems, Inc.
ICS1524
Dual Output Phase Controlled SSTL_3/PECL Clock Generator
General Description
Features
The ICS1524 is a low-cost, very high-performance • Wide input frequency range
frequency generator and phase controlled clock synthe-
• 8 kHz to 100 MHz
sizer. It is perfectly suited to phase controlled clock
synthesis and distribution as well as line-locked and
•
250 MHz balanced PECL differential outputs
genlocked applications.
• 150 MHz single-ended SSTL_3 clock outputs
• Dynamic Phase Adjust (DPA) for DPACLK
The ICS1524 offers two channels of clock phase con-
outputs
trolled outputs; CLK and DPACLK. These two output
• Software controlled phase adjustment
channels have both 250 MHz PECL differential and 150
• 360^o Adjustment down to 1/64 clock
MHz SSTL_3 single-ended output pins. The CLK output
increments
channel has a fixed phase relationship to the PLL’s input _{• External or internal loop filter selection}
and the DPACLK uses the Dynamic Phase Adjust cir-
cuitry to allow control of the clock phase relative to input
•
Uses 3.3 VDC Inputs are 5 volt tolerant.
signal.
• I²C-bus serial interface runs at either low speed
(100 kHz) or high speed (400 kHz).
Optionally, the CLK outputs can operate at half the clock
rate and phase aligned with the DPACLK channel, en-
abling deMUXing of multiplexed analog-to-digital
converters. The FUNC pin provides either the regener-
ated input from the phase-locked loop (PLL) divider
chain output or a re-synchronized and sharpened input
HSYNC.
The advanced PLL uses either its internal program-
mable feedback divider or an external divider and is
programmed by a standard I²C-bus™ serial interface.
• Hardware and Software PLL Lock detection
Applications
• Generic Frequency Synthesis
• LCD Monitors and Projectors
• Genlocking Multiple Video Systems
Block Diagram
Pin Configuration
HSYNC
OSC
I²C
Loop
Filter
CLK
CLK+/-
DPACLK
DPACLK+/-
FUNC
VDDD
1
VSSD
2
SDA
3
SCL
4
PDEN
5
EXTFB
6
HSYNC
7
EXTFIL
8
XFILRET
9
VDDA 10
VSSA 11
OSC 12
24
IREF
23
CLK+ (PECL)
22
CLK– (PECL)
21
DPACLK+ (PECL)
20
DPACLK– (PECL)
19
VSSQ
18
VDDQ
17
DPACLK (SSTL)
16
CLK
(SSTL)
15
FUNC (SSTL)
14
LOCK/REF (SSTL)
13
I²CADR
24 Pin 300-mil SOIC
I²C-bus is a trademark of Philips Corporation.
ICS1524 Rev C 01/31/2003
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.