ICS1524 Datasheet, PDF (6/24 Pages) Integrated Circuit Systems – Dual Output Phase Controlled SSTL-3/PECL Clock Generator

ICS1524
Detailed Register Description
Name:
Register:
Index:
Bit Name
Input Control
0h
Read / Write
Bit # Reset Value
Description
PDen
0
PD_Pol
1
Ref_Pol
2
Fbk_Pol
3
Fbk_Sel
4
Func_Sel
5
EnPLS
6
EnDLS
7
1
Phase detector Enable
0
Phase/Frequency Detector Input MUX Control
0
Phase/Frequency Detector External Reference Polarity
0
External Reference Feedback Polarity
0
External Feedback Select
0
Function Output Select
1
Enable PLL Lock Status Output on LOCK/REF pin
0
Enable DPA Lock Status Output on LOCK/REF pin
Bit Name
0 PDen
1 PD_Pol
Description
RESERVED
Input MUX Control
PD_POL
Bit 1
0
0
1
1
PDen
Pin 5
0
1
0
1
Phase/Frequency Detector
Input Supplied with...
OSC In
HSYNC In
HSYNC In
OSC In
2 Ref_Pol
Phase/Frequency Detector External Reference Polarity —
Edge of input signal on which Phase Detector triggers.
0 = Rising Edge (default)
1 = Falling Edge
3 Fbk_Pol
External Reference Feedback Polarity — Edge of EXTFB (pin 6) signal on which
Phase/Frequency Detector triggers when external feedback is used (Reg0 [4]=1).
0 = Positive Edge (default)
1 = Negative Edge
4 Fbk_Sel
External Feedback Select
0 = Internal Feedback (default)
1 = External Feedback
5 Func_Sel Function Output Select — Selects re-clocked output to FUNC (pin 15).
0 = Recovered HSYNC (default). Regenerated HSYNC output.
1 = External HSYNC. Schmitt-trigger conditioned input from HSYNC (pin 7).
6 EnPLS
Enable LOCK/REF (pin14) Output
7 EnDLS
EnPLS EnDLS IN_SEL
LOCK/REF(14)
0
0
N/A
0
0
1
N/A 1 if DPA locked, 0 otherwise
1
0
N/A 1 if PLL locked, 0 otherwise
1
1
0
Post Schmitt trigger
HSYNC(7) XOR Ref_Pol
1
1
1
F_osc ÷ Osc_Div
ICS1524 Rev C 01/31/2003
6