GMS81C2112 Datasheet, PDF (87/107 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112/GMS81C2120
20. POWER FAIL PROCESSOR
The GMS81C21xx has an on-chip power fail detection cir-
cuitry to immunize against power noise. A configuration
register, PFDR, can enable or disable the power fail detect
circuitry. Whenever V_DD falls close to or below power fail
voltage for 100ns, the power fail situation may reset or
freeze MCU according to PFDM bit of PFDR. Refer to
“7.4 DC Electrical Characteristics for Standard Pins(5V)”
on page 14.
In the in-circuit emulator, power fail function is not imple-
mented and user can not experiment with it. Therefore, af-
ter final development of user program, this function may
be experimented or evaluated.
Note: User can select power fail voltage level according to
PFD0, PFD1 bit of CONFIG register(703F_H) at the OTP
(GMS87C21xx) but must select the power fail voltage level
to define PFD option of “Mask Order & Verification Sheet”
at the mask chip(GMS81C21xx).
Because the power fail voltage level of mask chip
(GMS81C21xx) is determined according to mask option.
Note: If power fail voltage is selected to 3.0V on 3V oper-
ation, MCU is freezed at all the times.
Power FailFunction
Enable/Disable
Level Selection
OTP
PFDIS flag
PFS0 bit
PFS1 bit
MASK
PFDIS flag
Mask option
Table 20-1 Power fail processor
.
PFDR
R/W R/W R/W
7
6
5
4
3
2
1
0
PFDIS PFDM PFS
ADDRESS: 0EF_H
INITIAL VALUE: ---- -100_B
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
Operation Mode
0 : Normal operation regardless of power fail
1 : MCU will be reset by power fail detection
Disable Flag
0: Power fail detection enable
1: Power fail detection disable
Figure 20-1 Power Fail Voltage Detector Register
JUNE. 2001 Ver 1.00
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