GMS81C2112 Datasheet, PDF (75/107 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112/GMS81C2120
16.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.
Main Program
service
TIMER 1
service
Occur
TIMER1 interrupt
enable INT0
disable other
EI
Occur
INT0
INT0
service
enable INT0
enable other
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable "EI" in the TIMER1 routine.
Example: During Timer1 interrupt is in progress, INT0 in-
terrupt serviced without any suspend.
TIMER1: PUSH
PUSH
PUSH
LDM
LDM
EI
:
:
:
A
X
Y
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other
;Enable Interrupt
:
:
:
LDM
LDM
POP
POP
POP
RETI
IENH,#0F0H
IENL,#0F0H
Y
X
A
;Enable all interrupts
Figure 16-6 Execution of Multi Interrupt
JUNE. 2001 Ver 1.00
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