GMS81C2112 Datasheet, PDF (76/107 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112/GMS81C2120
16.4 External Interrupt
The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0F8_H) as shown in Figure 16-7.
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
INT1 pin
INT0 pin
INT1IF
INT1 INTERRUPT
INT0IF
22
INT0 INTERRUPT
IEDS
[0E6H]
Edge selection
Register
Figure 16-7 External Interrupt Block Diagram
INT0 and INT1 are multiplexed with general I/O ports
(R00 and R01). To use as an external interrupt pin, the bit
of R4 port mode register R0FUNC should be set to “1” cor-
respondingly.
Example: To use as an INT0 and INT1
:
:
;**** Set port as an input port R00,R01
LDM R0IO,#1111_1100B
;
;**** Set port as an interrupt port
LDM R0FUNC,#0000_0011B
;
;**** Set Falling-edge Detection
LDM IEDS,#0000_0101B
:
:
:
Response Time
The INT0 and INT1 edge are latched into INT0IF and
INT1IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a re-
quest is active and conditions are right for it to be acknowl-
edged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.
Figure 16-8shows interrupt response timings.
max. 12 f_XIN
8 f_XIN
Interrupt Interrupt
goes latched
active
Interrupt
processing
Interrupt
routine
Figure 16-8 Interrupt Response Timing Diagram
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JUNE. 2001 Ver 1.00