GMS81C2112 Datasheet, PDF (43/107 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112/GMS81C2120
10. BASIC INTERVAL TIMER
The GMS81C21xx has one 8-bit Basic Interval Timer that
is free-run, can not stop. Block diagram is shown in Figure
10-1. In addition, the Basic Interval Timer generates the
time base for watchdog timer counting. It also provides a
Basic interval timer interrupt (BITIF).
The 8-bit Basic interval timer register (BITR) is increased
every internal count pulse which is divided by prescaler.
Since prescaler has divided ratio by 8 to 1024, the count
rate is 1/8 to 1/1024 of the oscillator frequency. As the
count overflows from FF_H to 00_H, this overflow causes to
generate the Basic interval timer interrupt. The BITIF is in-
terrupt request flag of Basic interval timer. The Basic In-
terval Timer is controlled by the clock control register
(CKCTLR) shown in Figure 10-2.
When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL be-
comes "0" after one machine cycle by hardware.
If the STOP instruction executed after writing "1" to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
mode. In this mode, all of the block is halted except the os-
cillator, prescaler (only fXIN÷2048) and Timer0.
If the STOP instruction executed after writing "1" to bit
RCWDT of CKCTLR, it goes into the internal RC oscillat-
ed watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON de-
cides Watchdog Timer or the normal 7-bit timer.
Source clock can be selected by lower 3 bits of CKCTLR.
BITR and CKCTLR are located at same address, and ad-
dress 0EC_H is read as a BITR, and written to CKCTLR.
X_IN PIN
Internal RC OSC
WAKEUP
STOP
÷8
÷16
÷32
÷64
÷128
÷256
÷512
÷1024
MUX
Select Input clock ³
BTS[2:0]
[0EC_H]
Basic Interval Timer
clock control register
8-bit up-counter
1 source
clock
BITR
overflow
0
[0EC_H]
clear
RCWDT
CKCTLR
BTCL
Read
Internal bus line
BITIF
Basic Interval
Timer Interrupt
To Watchdog timer (WDTCK)
Figure 10-1 Block Diagram of Basic Interval Timer
JUNE. 2001 Ver 1.00
37