GMS81C2112 Datasheet, PDF (86/107 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112/GMS81C2120
19. RESET
The GMS81C21xx have two types of reset generation pro-
cedures; one is an external reset input, the other is a watch-
dog timer reset. Table 19-1 shows on-chip hardware ini-
tialization by reset action.
On-chip Hardware
Program counter
(PC)
RAM page register
G-flag
Operation mode
(RPR)
(G)
Initial Value
(FFFF_H) - (FFFE_H)
0
0
Main-frequency clock
On-chip Hardware
Peripheral clock
Watchdog timer
Control registers
Power fail detector
Initial Value
Off
Disable
Refer to Table 8-1 on page 27
Disable
Table 19-1 Initializing Internal Status by Reset Action
19.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, it is applied,
and the internal state is initialized. After reset, 64ms (at 4
MHz) add with 7 oscillator periods are required to start ex-
ecution as shown in Figure 19-2.
Internal RAM is not affected by reset. When V_DD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
When the RESET pin input goes to high, the reset opera-
tion is released and the program execution starts at the vec-
tor address stored at addresses FFFE_H - FFFF_H.
A connection for simple power-on-reset is shown in Figure
19-1.
V_CC
7036P
10kΩ
+
10uF
to the RESET pin
Figure 19-1 Simple Power-on-Reset Circuit
Oscillator
(X_IN pin)
RESET
1234567
ADDRESS
BUS
DATA
BUS
?
??
?
FFFE FFFF Start
?
? ? ? FE ADL ADH OP
Stabilization Time
t_ST = 62.5mS at 4.19MHz
RESET Process Step
1
t_ST = _{fMAIN ÷1024} x 256
MAIN PROGRAM
Figure 19-2 Timing Diagram after RESET
19.2 Watchdog Timer Reset
Refer to “11. WATCHDOG TIMER” on page 39.
80
JUNE. 2001 Ver 1.00