GMS81C2112 Datasheet, PDF (72/107 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112/GMS81C2120
.
INT0
INT1
Timer 0
Timer 1
A/D Converter
Watchdog Timer
BIT
Serial
Communication
Internal bus line
[0E2_H]
IRQH
[0E4_H]
INT0IF
INT1IF
T0IF
T1IF
IENH
Interrupt Enable
Register (Higher byte)
IRQL
[0E5_H]
ADIF
WDTIF
BITIF
SIOIF
I-flag is in PSW, it is cleared by "DI", set by
"EI" instruction. When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by "RETI" instruction, I-flag is set to
"1" by hardware.
Release STOP
I-flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
To CPU
[0E3_H]
IENL
Interrupt Enable
Register (Lower byte)
Internal bus line
Figure 16-2 Block Diagram of Interrupt
R/W R/W R/W R/W -
IENH INT0E INT1E ^T0E T1E
-
MSB
-
-
-
-
-
-
LSB
ADDRESS: 0E2_H
INITIAL VALUE: 0000 ----_B
R/W R/W R/W R/W -
IENL
ADE WDTE BITE SPIE
-
MSB
-
-
-
-
Timer/Counter 1 interrupt enable flag
Timer/Counter 0 interrupt enable flag
External interrupt 1 enable flag
External interrupt 0 enable flag
-
-
LSB
ADDRESS: 0E3_H
INITIAL VALUE: 0000 ----_B
Serial Communication interrupt enable flag
Basic Interval imer interrupt enable flag
Watchdog timer interrupt enable flag
A/D Convert interrupt enable flag
VALUE
0: Disable
1: Enable
Figure 16-3 Interrupt Enable Flag
66
JUNE. 2001 Ver 1.00