GMS81C2112 Datasheet, PDF (66/107 Pages) Hynix Semiconductor – HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C2112/GMS81C2120
Serial I/O Mode Register(SIOM) controls serial I/O func-
tion. According to SCK1 and SCK0, the internal clock or
external clock can be selected. The serial transmission op-
eration mode is decided by setting the SM1 and SM0, and
the polarity of transfer clock is selected by setting the POL.
Serial I/O Data Register(SIOR) is a 8-bit shift register.
First LSB is send or is received. When receiving mode, se-
rial input pin is selected by IOSW. The SPI allows 8-bits
of data to be synchronously transmitted and received.
To accomplish communication, typically three pins are
used:
- Serial Data In
- Serial Data Out
- Serial Clock
R54/SIN
R55/SOUT
R53/SCLK
.
SIOM
SIOR
R/W R/W R/W R/W R/W R/W R/W R
7
6
5
4
3
2
1
0
POL IOSW SM1 SM0 ^BSTCCKL1 SCK0 SIOST SIOSF
ADDRESS: 0E0_H
INITIAL VALUE: 0000 0001_B
Serial transmission status bit
0: Serial transmission is in progress
1: Serial transmission is completed
Serial transmission start bit
Setting this bit starts an Serial transmission.
After one cycle, bit is cleared to “0” by hardware.
Serial transmission Clock selection
00: f_XIN ÷ 4
01: f_XIN ÷ 16
10: TMR0OV(Timer0 Overflow)
11: External Clock
Serial transmission Operation Mode
00: Normal Port(R55,R54,R53)
01: Sending Mode(SOUT,R54,SCLK)
10: Receiving Mode(R55,SIN,SCLK)
11: Sending & Receiving Mode(SOUT,SIN,SCLK)
Serial Input Pin Selection bit
0: SIN Pin Selection
1: IOSWIN Pin Selection
R/W R/W R/W R/W R/W R/W R/W R/W
76543210
BTCL
Serial Clock Polarity Selection bit
0: Data Transmission at Falling Edge
Received Data Latch at Rising Edge
1: Data Transmission at Rising Edge
Received Data Latch at Falling Edge
ADDRESS: 0E1_H
INITIAL VALUE: Undefined
Sending Data at Sending Mode
Receiving Data at Receiving Mode
Figure 14-2 SPI Control Register
60
JUNE. 2001 Ver 1.00