HY29DL162 Datasheet, PDF (5/48 Pages) Hynix Semiconductor – 16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory

HY29DL162/HY29DL163
SIGNAL DESCRIPTIONS
Name
Type
Description
A[19:0]
Inputs
Address, active High. In word mode, these 20 inputs select one of 1,048,576
(1M) words within the array for read or write operations. In byte mode, these
inputs are combined with the DQ[15]/A[-1] input (LSB) to select one of 2,097,152
(2M) bytes within the array for read or write operations.
DQ[15]/A[-1],
DQ[14:0]
Data Bus, active High. In word mode, these pins provide a 16-bit data path
Inputs/Outputs for read and write operations. In byte mode, DQ[7:0] provide an 8-bit data path
Tri-state and DQ[15]/A[-1] is used as the LSB of the 21-bit byte address input. DQ[14:8]
are unused and remain tri-stated in byte mode.
BYTE#
Input
Byte Mode, active Low. Controls the Byte/Word configuration of the device.
Low selects Byte mode, High selects Word mode.
Chip Enable, active Low. This input must be asserted to read data from or
CE#
Input
write data to the HY29DL16x. When High, the data bus is tri-stated and the
device is placed in the Standby mode.
OE#
Input
Output Enable, active Low. This input must be asserted for read operations
and negated for write operations. BYTE# determines whether a byte or a word
is read during the read operation. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
WE#
Input
Write Enable, active Low. Controls writing of command sequences in order to
program data or erase sectors of the memory array. A write operation takes
place when WE# is asserted while CE# is Low and OE# is High. BYTE#
determines whether a byte or a word is written during the write operation.
RESET#
Input
Hardware Reset, active Low. Provides a hardware method of resetting the
HY29DL16x to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
RY/BY#
Output
Open Drain
Ready/Busy Status. Indicates whether a write or erase command is in
progress or has been completed. Valid after the rising edge of the final WE#
pulse of a command sequence. It remains Low while the device is actively
programming data or erasing, and goes High when it is ready to read array data.
Write Protect, active Low/Accelerate (V_HH).
Write Protect Function: Placing this pin at V_IL disables program and erase
operations in two of the eight 8 Kbyte/4 Kword boot sectors. The affected
sectors are S0 and S1 in a bottom-boot device, or S37 and S38 in a top-boot
device. If the pin is placed at V_IH, the protection state of those two sectors
reverts to whether they were last set to be protected or unprotected using the
method described in the Sector Group Protection and Unprotection sections.
WP#/ACC
Input
Accelerate Function: If V_HH is applied to this input, the device enters the Unlock
Bypass mode, temporarily unprotects any protected sectors, and uses the
higher voltage on the pin to reduce the time required for program operations.
The system would then use the two-cycle program command sequence as
required by the Unlock Bypass mode. Removing V_HH from the pin returns the
device to normal operation.
This pin must not be at V_HH for operations other than accelerated programming,
or device damage may result. Leaving the pin unconnected may result in
inconsistent device operation.
V_CC
--
3-volt (nominal) power supply.
V_SS
--
Power and signal ground.
r1.3/June 01
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