HY29DL162 Datasheet, PDF (18/48 Pages) Hynix Semiconductor – 16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory

HY29DL162/HY29DL163
Note: A hardware reset will reset the device to the read
array mode.
Program Command
The system programs the device a word or byte
at a time by issuing the appropriate four-cycle Pro-
gram command sequence, as shown in Table 10.
The sequence begins by writing two unlock cycles,
followed by the program setup command and,
lastly, the program address and data. This ini-
tiates the Automatic Program algorithm that auto-
matically provides internally generated program
pulses and verifies the programmed cell margin.
The host is not required to provide further con-
trols or timings during this operation. When the
Automatic Program algorithm is complete, that
bank returns to the Read mode. Several meth-
ods are provided to allow the host to determine
the status of the programming operation, as de-
scribed in the Write Operation Status section.
While the Automatic Program algorithm is in
progress in one bank, the host may read data from
the non-programming bank.
Commands written to the device during execution
of the Automatic Program algorithm are ignored.
Note that a hardware reset immediately terminates
the programming operation. To ensure data in-
tegrity, the aborted program command sequence
should be reinitiated once the reset operation is
complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored ‘0’ to a ‘1’.
Thus, a bit cannot be programmed from a ‘0’ back
to a ‘1’. Attempting to do so may cause that bank
to halt the operation and set DQ[5] to ‘1’, or cause
the Data# Polling algorithm to indicate the opera-
tion was successful. However, a succeeding read
will show that the data is still ‘0’.
Unlock Bypass/Bypass Program/Bypass Reset
Commands
Unlock Bypass provides a faster method than the
normal Program command for the host system to
program bytes or words to a bank. As shown in
Table 10, the Unlock Bypass command sequence
consists of two unlock write cycles followed by a
third write cycle containing the Unlock Bypass
command, 0x20. That bank then enters the Un-
lock Bypass mode. In this mode, a two-cycle Un-
lock Bypass Program command sequence is used
instead of the standard four-cycle program se-
quence to invoke a programming operation. The
first cycle in this sequence contains the Unlock
Bypass Program command, 0xA0, and the sec-
ond cycle specifies the program address and data,
thus eliminating the initial two unlock cycles re-
quired in the standard Program command se-
quence. Additional data is programmed in the
same manner.
During the Unlock Bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset com-
mands are valid. To exit the Unlock Bypass mode,
the host must issue the two-cycle Unlock Bypass
Reset command sequence shown in Table 10.
The bank specified in the first cycle of that com-
mand then returns to the Read array data mode.
Figure 4 illustrates the procedures for the normal
and unlock bypass program operations.
Note: The device automatically enters the Unlock By-
pass mode when it is placed in Accelerate mode via the
WP#/ACC pin.
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by a set-up command,
two additional unlock cycles and then the Chip
Erase command. This sequence invokes the Au-
tomatic Erase algorithm that automatically
preprograms (if necessary) and verifies the entire
memory for an all zero data pattern prior to elec-
trical erase. The host system is not required to pro-
vide any controls or timings during these operations.
If all sectors in the device are protected, the de-
vice returns to reading array data after approxi-
mately 100 µs. If at least one sector is unpro-
tected, the erase operation erases the unprotected
sectors, and ignores the command for the sectors
that are protected. However, even if every sector
in one of the banks is protected, reads from that
bank are not permitted until the completion of the
Automatic Erase algorithm for the unprotected
sectors in the other bank.
Commands written to the device during execution
of the Automatic Erase algorithm are ignored. Note
that a hardware reset immediately terminates the
chip erase operation. To ensure data integrity,
the aborted Chip Erase command sequence
should be reissued once the reset operation is
complete.
18
r1.3/June 01