HY29DL162 Datasheet, PDF (26/48 Pages) Hynix Semiconductor – 16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory

HY29DL162/HY29DL163
obtain valid erase status information on DQ[7]. If
all sectors designated for erasing are protected,
Data# Polling on DQ[7] is active for approximately
100 µs, then the bank returns to reading array data.
When the system detects that DQ[7] has changed
from the complement to true data (or “0” to “1” for
erase), it should do an additional read cycle to
ensure that valid data is read on DQ[7:0] or
DQ[15:0]. This is because DQ[7] may change
asynchronously with respect to the other data bits
while Output Enable (OE#) is asserted low.
Figure 7 shows the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Auto-
matic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be
read at any address within the programming or
erasing bank and is valid after the rising edge of
START
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data?
Test for DQ[7] = 1?
for Erase Operation
YES
NO
NO
DQ[5] = 1?
YES
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data?
(Note 2)
Test for DQ[7] = 1?
for Erase Operation
YES
NO
PROGRAM/ERASE
EXCEEDED TIME ERROR
PROGRAM/ERASE
COMPLETE
Notes:
1. During programming , the program address. During sector erase , an
address within any non-protected sector specified for erasure. During
chip erase , an address within any non-protected sector.
2. Recheck DQ[7] since it may change asynchronously to DQ[5].
the final WE# pulse in the Program or Erase com-
mand sequence, including during the sector erase
time-out. The system may use either OE# or CE#
to control the read cycles.
During an Automatic Program algorithm operation
(including programming while in Erase Suspend
mode), successive read cycles at any address in
the bank where the program operation is taking
place cause DQ[6] to toggle. DQ[6] stops tog-
gling when the operation is complete. If a pro-
gram address falls within a protected sector, DQ[6]
toggles for approximately 1 µs after the Program
command sequence is written, then returns to
reading array data.
While erasing, successive read cycles within any
sector designated for erasure (or any sector for
the chip erase operation) cause DQ[6] to toggle.
DQ[6] stops toggling when the erase operation is
complete or when the device is placed in the Erase
Suspend mode. The host may use DQ[2] to de-
termine which sectors are erasing or erase-sus-
pended (see below).
After an Erase command sequence is written, if
all the sectors designated for erasure are pro-
tected, DQ[6] toggles for approximately 100 µs,
and the device then returns to reading array data.
DQ[2] - Toggle Bit II
Toggle Bit II, DQ[2], when used with DQ[6], indi-
cates whether a particular sector is actively eras-
ing or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the
final WE# pulse in the command sequence. The
device toggles DQ[2] with each OE# or CE# read
cycle.
DQ[2] toggles when the host reads at addresses
within sectors that have been designated for era-
sure, but cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ[6],
by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but can-
not distinguish which sectors are designated for
erasure. Thus, both status bits are required for
sector and mode information.
Figure 8 illustrates the operation of Toggle Bits I
and II.
Figure 7. Data# Polling Test Algorithm
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r1.3/June 01