HY29DL162 Datasheet, PDF (19/48 Pages) Hynix Semiconductor – 16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory

START
NO
Enable Fast
Programming?
YES
Issue UNLOCK BYPASS
Command to Bank
Setup Next Address/Data for
Program Operation
NO
Bank in Unlock
Bypass Mode?
Issue NORMAL PROGRAM
Command
YES
Issue UNLOCK BYPASS
PROGRAM Command
HY29DL162/HY29DL163
Check Programming Status DQ[5] Error Exit
(See Write Operation Status
Section)
Programming Verified
NO
Last Word/Byte
Done?
YES
NO
Bank in Unlock
Bypass Mode?
YES
Issue UNLOCK BYPASS
RESET Command to Bank
PROGRAMMING
COMPLETE
GO TO ERROR
RECOVERY PROCEDURE
Figure 4. Normal and Unlock Bypass Programming Procedures
When the Automatic Erase algorithm is complete,
the device returns to the reading array data mode.
Several methods are provided to allow the host to
determine the status of the erase operation, as
described in the Write Operation Status section.
Figure 5 illustrates the chip erase procedure.
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by a set-up com-
START
Issue CHIP ERASE
Command Sequence
Check Erase Status
(See Write Operation Status
DQ[5] Error Exit
Section)
Normal Exit
CHIP ERASE COMPLETE
GO TO
ERROR RECOVERY
mand, two additional unlock cycles and then the
Sector Erase command, which specifies which
sector is to be erased. This sequence invokes
the Automatic Erase algorithm that automatically
preprograms (if necessary) and verifies the speci-
fied sector for an all zero data pattern prior to elec-
trical erase. The host system is not required to
provide any controls or timings during these op-
erations.
After the sector erase data cycle (the sixth cycle)
of the command sequence is issued, a sector
erase time-out of 50 µs (min) begins, measured
from the rising edge of the final WE# pulse in the
command sequence. During this time, an addi-
tional sector address and sector erase data cycle
may be written into an internal sector erase buffer.
This buffer may be loaded in any sequence, and
the number of sectors designated for erasure may
be from one sector to all sectors. The only re-
striction is that the time between these additional
cycles must be less than 50 µs, otherwise era-
sure may begin before the last address and com-
mand are accepted. To ensure that all commands
are accepted, it is recommended that host pro-
cessor interrupts be disabled during the time that
Figure 5. Chip Erase Procedure
r1.3/June 01
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