HY29DL162 Datasheet, PDF (2/48 Pages) Hynix Semiconductor – 16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory

HY29DL162/HY29DL163
GENERAL DESCRIPTION
The HY29DL162/HY29DL163 (HY29DL16x) is a
16 Mbit, 3 volt-only CMOS Flash memory orga-
nized as 2,097,152 (2M) bytes or 1,048,576 (1M)
words. The device is available in 48-pin TSOP
and 48-ball FBGA packages. Word-wide data
(x16) appears on DQ[15:0] and byte-wide (x8) data
appears on DQ[7:0].
The HY29DL16x Flash memory array is organized
into 39 sectors in two banks. Bank 1 contains
eight 8 Kbyte boot/parameter sectors and 3 or 7
larger sectors of 64 Kbytes each, depending on
the version of the device. Bank 2 contains the
rest of the memory array, organized as 28 or 24
sectors of 64 Kbytes:
HY29DL162
HY29DL163
Bank 1
8 x 8KB/4KW
3 x 64KB/32KW
8 x 8KB/4KW
7 x 64KB/32KW
Bank 2
28 x 64KB/32KW
24 x 64KB/32KW
The device features simultaneous read/write op-
eration which allows the host system to invoke a
program or erase operation in one bank and im-
mediately and simultaneously read data from the
other bank, except if that bank has any sectors
marked for erasure, with zero latency. This re-
leases the system from waiting for the completion
of program or erase operations, thus improving
overall system performance.
The HY29DL16x can be programmed and erased
in-system with a single 2.7 - 3.6 volt V_CC supply.
Internally generated and regulated voltages are
provided for program and erase operations, so that
the device does not require a higher voltage V_PP
power supply to perform those functions. The de-
vice can also be programmed in standard EPROM
programmers. Access times as low as 70 ns are
offered for timing compatibility with the zero wait
state requirements of high speed microproces-
sors. To eliminate bus contention, the HY29DL16x
has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single-
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte/word at
a time by executing the four-cycle Program Com-
mand write sequence. This initiates an internal
algorithm that automatically times the program
pulse widths and verifies proper cell margin. Faster
programming times can be achieved by placing
the HY29DL16x in the Unlock Bypass mode, which
requires only two write cycles to program data in-
stead of four.
The HY29DL16x’s sector erase architecture allows
any number of array sectors, in one or both banks,
to be erased and reprogrammed without affecting
the data contents of other sectors. Device erasure
is initiated by executing the Erase Command se-
quence. This initiates an internal algorithm that
automatically preprograms the sector before ex-
ecuting the erase operation. As during program-
ming cycles, the device automatically times the
erase pulse widths and verifies proper cell mar-
gin. Hardware Sector Group Protection option-
ally disables both program and erase operations
in any combination of the sector groups, while
Temporary Sector Group Unprotect, which re-
quires a high voltage on one pin, allows in-system
erasure and code changes in previously protected
sector groups. Erase Suspend enables the user
to put erase on hold in a bank for any period of
time to read data from or program data to any
sector in that bank that is not selected for era-
sure. True background erase can thus be
achieved. Because the HY29DL16x features si-
multaneous read/write capability, there is no need
to suspend to read from a sector located within a
bank that does not contain sectors marked for era-
sure. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles. The host system can detect comple-
tion of a program or erase operation by observing
the RY/BY# pin or by reading the DQ[7] (Data#
Polling) and DQ[6] (Toggle) status bits. Hardware
data protection measures include a low V_CC de-
tector that automatically inhibits write operations
during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another com-
2
r1.3/June 01