HY29DL162 Datasheet, PDF (36/48 Pages) Hynix Semiconductor – 16 Megabit (2M x 8/1M x16) Low Voltage, Dual Bank, Simultaneous Read/Write Flash Memory

HY29DL162/HY29DL163
AC CHARACTERISTICS
Program and Erase Operations
Parameter
JEDEC Std
Description
Speed Option
Unit
- 70 - 80 - 90 - 12
t_AVAV
t_WC Write Cycle Time ¹
Min 70 80 90 120 ns
t_AVWL
t_AS Address Setup Time
Min
0
ns
t_WLAX
t_AH Address Hold Time
Min 45 45 45 50 ns
t_AST Address Setup Time for Toggle Bit Test
Min
15
ns
t_AHT Address Hold Time for Toggle Bit Test
Min
0
ns
t_DVWH
t_DS Data Setup Time
Min 35 35 45 50 ns
t_WHDX
t_DH Data Hold Time
Min
0
ns
t_GHWL t_GHWL Read Recovery Time Before Write
Min
0
ns
t_ELWL
t_CS CE# Setup Time
Min
0
ns
t_WHEH
t_CH CE# Hold Time
Min
0
ns
t_OEPH OE# High Time for Toggle Bit Test
Min
20
ns
t_CEPH CE# High Time for Toggle Bit Test
Min
20
ns
t_WLWH
t_WP Write Pulse Width
Min 30 30 35 50 ns
t_WHWL t_WPH Write Pulse Width High
Min
30
ns
t_SR/W Latency Between Read and Write Operations
Min
0
ns
Typ
10
µs
Byte Mode
Max
150
µs
Programming Operation ^{1, 2, 3}
Typ
15
µs
t_WHWH1
t_WHWH1
Word Mode
Max
210
µs
Accelerated Programming
Byte or Typ
10
µs
Operation ^{1, 2, 3} (WP#/ACC = V_HH)
Word Mode Max
150
µs
Typ
20
sec
Byte Mode
Chip Programming Operation ^{1, 2, 3, 5}
Max
60
sec
Typ
16
sec
Word Mode
Max
48
sec
t_WHWH2 t_WHWH2 Sector Erase Operation ^{1, 2, 4}
Typ
0.5
sec
Max
7.5
sec
t_WHWH3
t_WHWH3 Chip Erase Operation ^{1, 2, 4}
Erase and Program Cycle Endurance ¹
Typ
16
sec
Typ
1,000,000
cycles
Min
100,000
cycles
t_VCS V_CC Setup Time ¹
Min
50
µs
t_RB Recovery Time from RY/BY#
Min
0
ns
t_BUSY WE# High to RY/BY# Delay
Min
90
ns
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 °C, V = 2.0 volts, 100,000 cycles. In addition,
CC
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-
tions of 90 °C, V_CC = 1.8 volts, 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the Program
command. See Table 10 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes/words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the
maximum byte/word program time specified is exceeded. See Write Operation Status section for additional information.
36
r1.3/June 01