HMC700LP4 Datasheet, PDF (8/36 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N PLL

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HMC701LP6CE
8 GHz 16-Bit Fractional-N PLL
Sine Reference Input
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The crystal reference sine input stage is shown in Figure 2. This is the lowest noise reference path. This is a common
emitter single ended bipolar buffer. The XSIN input pin is DC coupled and has about 950 mV bias on it. Expected
input is a 0 dBm sinusoid from a 50 Ohm source. Normally the input should be AC coupled externally. The sine buffer
input impedance is dominated by a 25 Ohm shunt resistor in series with a 50 pF on chip cap. Should a lower input
impedance be needed, an external 50 Ohm shunt resistor can be used, DC isolated by an external bypass cap. The
sine input reference path phase noise floor is approximately equivalent to -159 dBc/Hz. For best performance care
should be taken to provide a crystal reference source with equivalent or better phase noise floor.
Figure 2. Ref Sine Input
Square Wave Reference Input
The square wave Ref Input stage is shown in Figure 3. The stage is designed to accept square wave inputs from CML
to CMOS levels. Slightly degraded phase noise performance may be obtained with quasi sine 1 Vpp inputs. It may be
necessary to attenuate very large CMOS levels if absolute best in close phase noise performance is required. Input
reference should have a noise floor better than -160 dBc/Hz to avoid degradation of the input reference path.
Figure 3. Square Wave Ref Input Stage
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