HMC700LP4 Datasheet, PDF (10/36 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N PLL

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HMC701LP6CE
8 GHz 16-Bit Fractional-N PLL
RF Input Stage
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The synthesizer RF input stage routes the external VCO to the phase detector via a 16-bit fractional divider. The RF
input path is rated to operate nominally from 100 kHz to 8 GHz in fractional and 9 GHz in integer modes. The RF input
stage also provides isolation between the VCO and the prescaler. The RF input stage is a differential common emitter
stage, DC coupled for maximum flexibility. The input is protected by ESD diodes as shown in Figure 5. Normally the
RF input is AC coupled to a single ended external source. The RFINP buffer is well matched from a single ended
50 Ohm source above about 3.5 GHz, with the complimentary input grounded. If a better match is required at low
frequency a simple shunt 50 Ohm resistor can be used external to the package. If a differential external source is used
then the two input pins may be used for best performance.
Figure 5. RF Input Stage
RF Path ’N’ Divider
The main RF path divider is capable of average divide ratios between 65,531 and 36 in fractional mode, and 65,535
to 32 in integer mode. The reason for the difference between integer and fractional modes is that the fractional divider
actually divides by up to ±4 from the average divide number. Actual division ratios when used with a given VCO will
depend upon the reference frequency used and the desired output band.
General Purpose Output (GPO) Interface
The HMC701LP6CE features a 3-wire General Purpose Output (GPO) interface. GPO registers are described in
Reg1Bh Table 37. The GPO is a flexible interface that supports a number of different functions and real time waveform
access including:
a. General Data Output from SPI register gpo_sel_0_
data (gpo_sel=0)
e. Internal synchronized frac strobe with clocks
(gposel=4)
b. Prescaler & reference path outputs (gpo_sel=1)
f. Δ∑ Modulator Phase Accumulator (gposel=6)
c. Lock Detect Windows (gpo_sel=2)
g. Auxiliary oscillators (gposel=7)
d. Anti-cycle Slip waveforms (gpo_sel=3)
h. Δ∑ Modulator Outputs (gposel=10)
General Data to GPO (gpo_sel=0)
Setting register gpo_sel=0 in Table 37 assigns the 3-bit data from register gpo_sel_0_data Reg1B<6:4> to the GPO
bus.
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [e-mail]
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