HMC700LP4 Datasheet, PDF (32/36 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N PLL

v07.0411
HMC701LP6CE
8 GHz 16-Bit Fractional-N PLL
Table 34. Reg 18h Auxiliary Oscillator Register 1
Bit
Type
Name
Default
1:0
R/W dsmclk_auxclk_insel
0
3:2
R/W dsmclk_auxclk_modesel
0
6:4
R/W dsmclk_auxclk_divsel
2
7
R/W dsmclk_auxclk_sel
0
8
R/W dsmclk_auxmod_lfsr_en
0
9
R/W dsmclk_auxmod_accum_en
0
11:10
R/W dsmclk_auxmod_mode
0
19:12
R/W dsmclk_auxmod_fracstep
3
22:20
R/W dsmclk_auxmod_lodly
0
Description
Selects the input clk for auxclk
0:vcodiv
1:xrefsq or sin
2:refdiv
3:ring oscillator from mono, est 300 MHz to
1 GHz
0: bypass-no delay
1: pass through w/ delay
2: ring-out constant
3: ring-out seeded/gated
divider selection auxclk value divby
000 1
001 2
010 4
011 6
100 8
101 10
110 12
111 14
selects auxclk (if=1) as natural reference clk
input of sigma delta
enables 10-bit lfsr inside the delay modulator
(clocked by auxclk or auxclkb)
enables 8-bit accumulator inside the delay
modulator (clocked by auxclk or auxclkb)
delay modulation mode
0: auxmod_lodly_in passthrough
1: accumulator based square-wave
2: lfsr (lo-amp)
3: lfsr (hi-amp)
step-size of accumulator (changes square-wave
value once it wraps through 256)
value of delay-element (when auxmod_mode=0)
or low value used during sq-wave modulation
Table 35. Reg 19h Auxiliary Oscillator Register 2
Bit
Type
Name
Default
2:0
R/W dsmclk_auxmod_hidly
7
3
R/W dsmclk_auxmod_clkinv
1
4
R/W dsmclk_auxmod_clkwring
9
Description
hi value of delay element during sq-wave
modulation
optionally inverts auxclk as used by the
modulator
select LKD ringosc to clock the LFSR
0
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