HMC700LP4 Datasheet, PDF (20/36 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N PLL

v07.0411
HMC701LP6CE
8 GHz 16-Bit Fractional-N PLL
Example 2: Set the output to 4.600 025 GHz using a 100 MHz reference, R=2.
Find the nearest integer value, N_int, N_int = 92, f_int = 4.600 000 GHz
This leaves the fractional part to be f_frac =25 kHz
0
(EQ 15)
Since N_frac must be an integer number, the actual fractional frequency will be 25,001.17 Hz, an error of 1.17 Hz.
Here we program the 16-bit N_int = 92d = 5Ch = 0000 0000 0101 1100 and
the 24-bit N_frac = 8389d = 20C5h = 0000 0010 0000 1100 0101
In addition to the above frequency programming words, the fractional mode must be enabled using the frac register.
Other DSM configuration registers should be set to the recommended values. Register setup files are available on
request.
Integer Frequency
The synthesizer is capable of operating in integer mode. In integer mode the digital Δ∑ modulator is normally shut
off and the division ratio of the VCO divider is set at a fixed value. To run in integer mode set dsm_integer_mode
(Reg12h<3> Table 29) and clear dsm_rstb (Reg01h<13> Table 12). Then program the integer portion of the frequency,
N_INT, as explained by (EQ 13), ignoring the fractional part.
Frequency Hopping Trigger
If the synthesizer is in fractional mode, a write to the fractional frequency register, Reg10h Table 27, will initiate the
frequency hop on the falling edge of the 31^st clock edge of the serial port write (see Figure 18).
If the integer frequency register, Reg0Fh Table 26, is written when in fractional mode the information will be buffered
and only executed when the fractional frequency register is written.
If the synthesizer is in integer mode, a write to the integer frequency register, Reg0Fh Table 26, will initiate the
frequency hop on the falling edge of the 31^st clock edge of the serial port write (see Figure 18).
Power On Reset (POR)
Normally all logic cells in the HMC701LP6CE are reset when the device digital power supply, DVDD, is applied. This
is referred to as Power On Reset, or just POR. POR normally takes about 500us after the DVDD supply exceeds 1.5V,
guaranteed to be reset in 1msec. Once the DVDD supply exceeds 1.5V, the POR will not reset the digital again unless
the supply drops below 100mV.
Soft Reset
The SPI registers may also be soft reset by an SPI write to strobe global_swrst_regs (Reg00h<0> Table 11).
All other digital, including the fractional modulator, may be reset with an SPI write to strobe global_swrst_dig
(Reg00h<1> Table 11).
Hardware Reset
The SPI registers may also be hardware reset by holding RSTB, pin 19, low.
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978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [e-mail]
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