HMC700LP4 Datasheet, PDF (25/36 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N PLL

v07.0411
HMC701LP6CE
8 GHz 16-Bit Fractional-N PLL
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MAIN SERIAL PORT
The HMC701LP6CE features a four wire serial port for simple communication with the host controller. Register types
may be Read Only, Write Only, Read/Write or Strobe, as described in the registers descriptions. The synthesizer also
features an auxiliary 3-wire serial port, known as the VCO Serial Port. The VCO Serial Port is a write only interface
from the synthesizer to an optional switched resonator VCO that supports 3-wire serial port control.
Typical main serial port operation can be run with SCLK at speeds up to 50 MHz. Serial port registers are described
in the section REGISTER MAP.
Serial Port WRITE Operation
AVDD = DVDD = 3V ±10%, AGND = DGND = 0V
Table 4. Timing Characteristics
Parameter
Conditions
t₁
SEN to SCLK setup time
t₂
SDI to SCLK setup time
t₃
SDI to CLK hold time
t₄
SCLK high duration
t₅
SCLK low duration
t₆
SEN High duration
t₇
SEN low duration
Min.
8
10
10
8
8
640
20
Typ.
Max
Units
nsec
nsec
nsec
nsec
nsec
nsec
nsec
A typical WRITE cycle is shown in Figure 18.
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE
cycle, followed by a rising edge of SCLK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCLK after SEN. SDI low initiates
the WRITE cycle (/WR)
c. Host places the six address bits on the next six falling edges of SCLK, MSB first.
d. Slave registers the address bits in the next six rising edges of SCLK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first .
f. Slave registers the data bits on the next 24 rising edges of SCK (8-31).
g. SEN is de-asserted on the 32nd falling edge of SCLK.
h. The 32^nd rising edge of SCLK completes the cycle
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Figure 18. Serial Port Timing Diagram - WRITE
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