HMC700LP4 Datasheet, PDF (30/36 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N PLL

v07.0411
HMC701LP6CE
8 GHz 16-Bit Fractional-N PLL
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Table 26. Reg 0Fh Integer Division Register
Bit
Type
Name
Default
Description
15:0
R/W dsm_intg
200d
unsigned integer portion of VCO divider value,
also known as N_INT, see (EQ 12)
Table 27. Reg 10h Fractional Division Register
Bit
Type
Name
Default
23:0
R/W dsm_frac
0
Description
unsigned fractional portion of VCO divider also
known as N_FRAC, see (EQ 12)
Table 28. Reg 11h Seed Register
Bit
Type
Name
23:0
R/W dsm_seed
Default
0
Description
unsigned seed value for Δ∑ modulator
sets the start phase of the modulator
Table 29. Reg 12h Delta Sigma Modulator Register
Bit
Type
Name
0
R/W dsm_ref_clk_select
1
R/W dsm_invert_clk_sd3
2
R/W dsm_invert_clk_rph
Default
0
1
0
Description
use reference instead of divider
invert Δ∑ clk
inverts the ref clock phase
3
R/W dsm_integer_mode
1- enables Integer Mode, bypasses the Δ∑
0
modulator, leaves it running
see also dsm_rstb Reg01h<13> to disable the
modulator
4
R/W Reserved
0
5
6
7
9:8
13:10
17:14
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
dsm_xref_sin_select
dsm_autoseed
dsm_order
dsm_quant_max
dsm_quant_min
0
0
1
2
4’b0111
4’b1000
when xref is selected specifies that the sine
source is used
automatic seed load when changing the frac
part, uses value in seed
00-first order 01-second 10-third fb 11-third ff
max value allowed out of Δ∑ modulator quantizer
limits are +7 to -8, typ ±3 or ±4
min value allowed out of Δ∑ modulator quantizer
limits are +7 to -8, typ ±3 or ±4
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