HMC700LP4 Datasheet, PDF (12/36 Pages) Hittite Microwave Corporation – 8 GHz 16-Bit Fractional-N PLL

v07.0411
HMC701LP6CE
8 GHz 16-Bit Fractional-N PLL
Anti-cycle Slip Waveforms (gpo_sel = 3)
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Setting register gpo_sel=3 (Reg1Bh<3:0> Table 37) gives visibility into the anti-cycle slipping function of the PFD
as described in section Cycle Slip Prevention (CSP). Three waveforms, reference path freq > VCO path freq, vco
path freq > ref path freq, and a PFD strobe which holds the PFD at maximum gain, are routed to GPO3, GPO2, and
GPO1 respectively. These lines will be active during frequency pull-in and will indicate instantaneously which signal,
reference or vco path is greater in frequency. The PFD strobe gives insight into when the PFD is near maximum gain
at 2π. The PFD strobe will be active until the VCO pulls into lock.
Internal Synchronized Frac strobe with clocks (gpo_sel= 4)
Setting register gpo_sel=4 in (Reg1Bh<3:0> Table 37) gives visibility into the internally synchronized strobe that
is generated when commanding a frequency change by writing to the frac register. The internal strobe initiates the
update to the fractional modulator. The internal frac strobe, the ref path divider output and the sine reference input are
buffered out to GPO1,GPO2 and GPO3 respectively as shown in Figure 8. In this mode, GPO1 may be used to trigger
an external instrument when doing frequency hopping tests for example.
Figure 8. gpo_04 Outputs
Δ∑ Modulator Phase Accumulator (gpo_sel=6)
Setting register gpo_sel=6 (Reg1Bh<3:0> Table 37) assigns the three msb’s of the delta sigma modulator first
accumulator to GPO<3:1>, where GPO3 is the msb. This feature provides insight into the phase of the VCO.
Auxiliary Oscillators (gpo_sel=7)
Setting register gpo_sel=7 (Reg1Bh<3:0> Table 37) assigns an auxiliary clock, an internal ring oscillator, and the
internal sigma delta clock to GPO3, 2, 1 respectively. The control of the auxiliary clock is determined by Reg18h Table
34 and Reg19h Table 35. In general terms, this highly flexible clock source allows the selection of one of the various
VCO or crystal related clocks inside the synthesizer or the selection of a flexible unstabilized auxiliary ring oscillator
clock. Any of the sources may be routed out via gpo_sel=7. Additional Reg18h Table 34 clock controls allow the aux
clock to be delayed by a variable amount (auxclk_modesel Reg18h<3:2>), or to be divided down by even values from
2 to 14 (auxclk_divsel Reg18h<6:4>).
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