HD66760 Datasheet, PDF (92/105 Pages) Hitachi Semiconductor – 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors

HD66760
Clock Synchronized Serial Interface Timing Characteristics
(Vcc = 2.2 to 3.6 V)
Item
Serial clock cycle time
Serial clock high-level pulse width
Serial clock low-level pulse width
Serial clock rise/fall time
CS* Setup time
CS* hold time
Serial input data setup time
Serial input data hold time
Serial output data delay time
Serial output data hold time
Symbol Min
t _SCYC
142
330
t _SCH
50
130
t _SCL
50
130
t_SCr , t_SCf —
t _CSU
20
60
t _CH
100
60
t _SISU
40
t _SIH
40
t _SOD
—
t _SOH
0
Typ Max Unit Test Condition
—
—
ns
Figure 70
—
—
ns
Figure 71
—
—
ns
Figure 70
—
—
ns
Figure 71
—
—
ns
Figure 70
—
—
ns
Figure 71
—
25
ns
Figure 70, 71
—
—
ns
Figure 70
—
—
ns
Figure 71
—
—
ns
Figure 70
—
—
ns
Figure 71
—
—
ns
Figure 70
—
—
ns
Figure 70
—
130 ns
Figure 71
—
—
ns
Figure 71
I2C Bus Interface Timing Characteristics
(Vcc = 2.2 to 3.6 V)
Item
SCL clock frequency
SCL clock high-level pulse width
SCL clock low-level pulse width
SCL/SDA rise time
SCL/SDA fall time
Bus free time
Start condition hold time
Setup time for a repeated START
condition
Setup time for STOP condition
SDA data setup time
SDA data hold time
SCL/SDA spike pulse width
Symbol Min
f _SCL
t _SCLH
t _SCLL
t _Sr
t _Sf
t _BUF
t _STAH
t _STAS
0
120
240
10
10
240
320
320
t _STOS
t _SDAS
t _SDAH
t _SP
320
40
0
0
Typ Max Unit Test Condition
— 1300 kHz Figure 72
—
—
ns
Figure 72
—
—
ns
Figure 72
—
160 ns
Figure 72
—
70
ns
Figure 72
—
—
ns
Figure 72
—
—
ns
Figure 72
—
—
ns
Figure 72
—
—
ns
Figure 72
—
—
ns
Figure 72
—
—
ns
Figure 72
—
10
ns
Figure 72