HD66760 Datasheet, PDF (48/105 Pages) Hitachi Semiconductor – 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors

HD66760
a) Basic data-send timing through the clock synchronized serial interface
Transfer start
CS*
Transfer end
SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SDA
"0" "1" "1" "1" "0" ID RS "1" D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Device ID code
RS RW
1st data
2nd data
Start byte
b) 1st and 2nd byte assignment
1st byte
D7 D6 D5 D4 D3 D2 D1 D0
Status / read data register
2nd byte
D7 D6 D5 D4 D3 D2 D1 D0
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
Status / read data register
upper bits
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Status / read data register
lower bits
c) Consecutive data-send timing through the clock synchnorized serial interface
CS*
SCL
SDA
Start byte
(SR or R00h read)
Dummy read
(1 byte)
Status or device code Status or device code
upper bits (1 byte)
lower bits(1 byte)
When status is read, valid data can be read after one dummy read cycle.
SDA
Start byte (RS=1)
Dummy read
(5 bytes)
Read data upper bits Read data lower bits
(1 byte)
(1 byte)
When GRAM data is read, valid data can be read after five dummy read cycles.
Status lower bits
(1 byte)
Read data lower bits
(1 byte)
Figure 30b Clock synchronized serial interface data-send sequence