HD66760 Datasheet, PDF (102/105 Pages) Hitachi Semiconductor – 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors

HD66760
80-system Bus Operation
RS
CS*
WR*
RD*
*2
DB0
to DB15
*2
DB0
to DB15
VIH
VIL1
VIH
VIL1
tAS
tAH
VIH
VIL1
*1
PWLW, PWLR
PWHW, PWHR
VIH
VIH
VIH
VIL1
VIL1
tWRr
tWRf
tCYCW, tCYCR
tDSW
tHWR
VIH
VIL1
Write data
VIH
VIL1
tDDR
VOH1
VOL1
tDHR
Read data
VOH1
VOL1
Note: 1. PWLW and PWLR are specified in the overlapped period when CS* is low and WR* or RD* is low.
2. Parallel data transfer is enabled on the DB15-8 pins when the 8-bit bus interface is used.
Fix tje DB7-0 pins to Vcc or GND.
Figure 68 80-system Bus Timing
Reset Operation
tRES
RESET*
VIL1
VIL1
Figure 69 Reset Timing