HD66760 Datasheet, PDF (38/105 Pages) Hitachi Semiconductor – 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors

HD66760
Table 28 Instruction List
Upper Code
Lower Code
Reg. Register
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
No. Name R/W RS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Description
Execu-
tion
Cycle
IR Index
0
0
**
**
*
**
* * ID6 ID5 ID4 ID3 ID2 ID1 ID0 Sets the index register value.
0
SR Status
read
1
0
0 L6 L5 L4 L3 L2 L1 L0 0 C6 C5 C4 C3 C2 C1 C0 Reads the driving raster-row
0
position (L7–0) and contrast setting
(C6–0).
R00h Start
0
1
**
**
*
**
**
*
**
**
*
1 Starts the oscillation mode.
oscillation
10 ms
Device
1
1
10
00
0
11
10
1
10
00
0
0 Reads 8760h
0
code read
R01h Driver
output
control
0
1
00
00
0
0 CMS SGS 0
0
0 0 NL3 NL2 NL1 NL0 Sets the common driver shift
0
direction (CMS), segment driver
shift direction (SGS), and driving
duty ratio (NL3–0).
R02h LCD-
0
1
00
00
0
0 0 RST 0 B/C EOR NW4 NW3 NW2 NW1 NW0 Software reset (RST), LCD drive AC 10 tcyc
driving-
waveform (B/C), EOR output (EOR),
waveform
and the number of n-raster-rows
control
(NW4–0) at C-pattern AC drive.
R03h Power
control
0
1
00
0 BS2 BS1 BS0 BT1 BT0 PS1 PS0 DC1 DC0 AP1 AP0 SLP STB Sets the sleep mode (SLP), standby 0
mode (STB), LCD power on (AP1–
0), boosting cycle (DC1–0), boosting
output multiplying factor (BT1–0),
and LCD drive bias value (BS2–0).
R04h Contrast
0
1
00
00
0 VR2 VR1 VR0 0 CT6 CT5 CT4 CT3 CT2 CT1 CT0 Sets the contrast adjustment
0
control
(CT6–0) and regulator adjustment
(VR2–0).
R05h Entry
mode
0
1
00
00
0
0 0 SWP 0
0
0 I/D AM LG2 LG1 LG0 Specifies the logical operation
0
(LG2–0), AC counter mode (AM),
increment/decrement mode (I/D),
and swap (SWP).
R06h Compare 0
1
00
00
0
00
0 CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0 Sets the compare register (CP7–0). 0
register
R07h Display
control
0
1
00
00
0 VLE VLE SPT 0
0
E B/W GS REV D1 D0 Specifies display on (D1–0),
0
21
reversed display (REV), 4-/16-
grayscale mode (GS), pixel mode
enable (E), pixel on/off (B/W),
screen division driiving (SPT), and
vertical scroll (VLE2–1).
R08h Cursor
control
01
0
00
0 0 CR CG CB 0 0
0
C0
0 CM1 CM0 Specifies cursor display on (C),
cursor display mode (CM1–0), and
cursor color (CR, CG, or CB).
R09h Grayscale 0 1
0
00
00
0
00
00
0
00
00
0 Synchronizes the grayscale with the 0
and blink
blink cycle.
synchroni-
zation
R11h Vertical
scroll
control
01
0 VL26 VL25 VL24 VL23 VL22 VL21 VL20 0 VL16 VL15 VL14 VL13 VL12 VL11 VL10 Specifies the 1st-screen display-
0
start raster-row (VL16–10) and 2nd-
screen display-start raster-row
(VL26–20).
R12h Horizontal 0
1
0 HE6 HE5 HE4 HE3 HE2 HE1 HE0 0 HS6 HS5 HS4 HS3 HS2 HS1 HS0 Sets horizontal cursor start (HS6–0) 0
cursor
and end (HE6–0).
position
R13h Vertical
cursor
position
0
1
0 VE6 VE5 VE4 VE3 VE2 VE1 VE0 0 VS6 VS5 VS4 VS3 VS2 VS1 VS0 Sets vertical cursor start (VS6–0) 0
and end (VE6–0).
R14h 1st screen 0
1
0 SE SE SE SE SE SE SE 0 SS SS SS SS SS SS SS Sets 1st-screen driving start
0
driving
16 15 14 13 12 11 10
16 15 14 13 12 11 10 (SS16–10) and end (SE16–10).
position
R15h 2nd screen 0
1
0 SE SE SE SE SE SE SE 0 SS SS SS SS SS SS SS Sets 2nd-screen driving start
0
driving
26 25 24 23 22 21 20
26 25 24 23 22 21 20 (SS26–20) and end (SE26–20).
position
R20h RAM write 0
data mask
1 WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM Specifies write data mask (WM15– 0
15 14 13 12 11 10 9
87
6
54
32
1
0 0) at RAM write.