HD66760 Datasheet, PDF (12/105 Pages) Hitachi Semiconductor – 104 X 80-dot Graphics LCD Controller/Driver for 256 Colors

HD66760
Address Counter (AC)
The address counter (AC) assigns addresses to the GRAM. When an address set instruction is written into the
IR, the address information is sent from the IR to the AC.
After writing into the GRAM, the AC is automatically incremented by 1 (or decremented by 1). After reading
from the data, the AC is not updated.
Graphics RAM (GRAM)
The graphics RAM (GRAM) has eight bits/pixel and stores the bit-pattern data of 104 × 80 bytes.
Grayscale Palette (GSP)
The grayscale palette (GSP) is a palette table that converts the information (three bits for each color: two bits
for B) read from the GRAM to 4-bit grayscale data. Any 256 of the 4,096 possible colors can be displayed at
the same time. For details, see the Grayscale Palette section.
Grayscale Control Circuit
The grayscale control circuit performs 16-grayscale control with the frame rate control (FRC) method for
grayscale display for each color. For details, see the Grayscale Palette section.
Timing Generator
The timing generator generates timing signals for the operation of internal circuits such as the GRAM. The
RAM read timing for display and internal operation timing by MPU access are generated separately to avoid
interference with one another.
Oscillation Circuit (OSC)
The HD66760 can provide R-C oscillation simply through the addition of an external oscillation-resistor
between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size,
and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be
supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be
reduced. For details, see the Oscillation Circuit section.
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 80 common signal drivers (COM1 to COM80) and 312
segment signal drivers (SEG1 to SEG312). When the number of lines are selected by a program, the required
common signal drivers automatically output drive waveforms, while the other common signal drivers
continue to output unselected waveforms.
Display pattern data is latched when 312-bit data has arrived. The latched data then enables the segment
signal drivers to generate drive waveform outputs. The shift direction of 312-bit data can be changed by the
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